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ADVANCE INFORMATION
PE9702
Product Description
Peregrine's PE9702 is a high-performance integer-N PLL capable of frequency synthesis up to 3.0 GHz. The device is designed for superior phase noise performance while providing an order of magnitude reduction in current consumption, when compared with existing commercial space PLLs. The PE9702 features a 10/11 dual modulus prescaler, counters and a phase comparator as shown in Figure 1. Counter values are programmable through either a serial or parallel interface and can also be directly hard wired. The PE9702 is optimized for commercial space applications. Single Event Latch up (SEL) is physically impossible and Single Event Upset (SEU) is better than 10-9 errors per bit / day. Fabricated in Peregrine's patented UTSi(R) (Ultra Thin Silicon) CMOS technology, the PE9702 offers excellent RF performance and intrinsic radiation tolerance. Figure 1. Block Diagram
3.0 GHz Integer-N PLL for Rad Hard Applications
Features * 3.0 GHz operation * /10/11 dual modulus prescaler * Internal phase detector * Serial, parallel or hardwired programmable * Ultra-low phase noise * SEU < 10-9 errors / bit-day * 100 Krad (Si) total dose * 44-lead CQFJ
Fin Fin
Prescaler 10 / 11
Main Counter 13
fp
D(7:0) 8 Sdata Pre_en M(6:0) A(3:0) R(3:0) fr
Primary 20-bit 20 Latch
Secondary 20-bit Latch
20 20
20 16
Phase Detector
PD_U PD_D
6
6 fc
R Counter
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Figure 2. Pin Configuration
GND GND GND Enh VDD LD R3 R2 R1 R0 fr
6
D0, M0 D1, M1 D2, M2 D3, M3 VDD VDD S_WR, D4, M4 Sdata, D5, M5 Sclk, D6, M6 FSELS, D7, Pre_en GND
5
4
3
2
1
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
fc VDD_fc PD_U PD_D VDD Cext VDD Dout VDD_fp fp GND
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
FSELP, A0 E_WR, A1 M2_WR, A2 Smode, A3 Bmode VDD M1_WR A_WR Hop_WR Fin Fin
Table 1. Pin Descriptions
Pin No.
1 2 3 4 5 6 7 8
Pin Name
VDD R0 R1 R2 R3 GND D0 M0 D1 M1
Interface Mode
ALL Direct Direct Direct Direct ALL Parallel Direct Parallel Direct Parallel Direct Parallel Direct ALL ALL Serial
Type
(Note 1) Input Input Input Input (Note 1) Input Input Input Input Input Input Input Input (Note 1) (Note 1) Input
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing recommended. R Counter bit0 (LSB). R Counter bit1. R Counter bit2. R Counter bit3. Ground. Parallel data bus bit0 (LSB). M Counter bit0 (LSB). Parallel data bus bit1. M Counter bit1. Parallel data bus bit2. M Counter bit2. Parallel data bus bit3. M Counter bit3. Same as pin 1. Same as pin 1. Serial load enable input. While S_WR is "low", Sdata can be serially clocked. Primary register data is transferred to the secondary register on S_WR or Hop_WR rising edge.
File No. 70/0036~00C |
9
D2 M2
10
D3 M3
11 12 13
VDD VDD S_WR
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PE9702
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Pin No.
Pin Name
D4 M4 Sdata
Interface Mode
Parallel Direct Serial Parallel Direct Serial Parallel Direct Serial Parallel Direct ALL Parallel Direct Serial
Type
Input Input Input Input Input Input Input Input Input Input Input Parallel data bus bit4 M Counter bit4
Description
Binary serial data input. Input data entered MSB first. Parallel data bus bit5. M Counter bit5. Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR "low") or the 8-bit enhancement register (E_WR "high") on the rising edge of Sclk. Parallel data bus bit6. M Counter bit6. Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for programming of internal counters while in Serial Interface Mode. Parallel data bus bit7 (MSB). Prescaler enable, active "low". When "high", Fin bypasses the prescaler. Ground.
14
D5 M5 Sclk
15
D6 M6 FSELS
16
D7
Pre_en
17
GND FSELP A0
18
Input Input Input Input Input Input Input Input Input Input (Note 1) Input Input Input Input Input
Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for programming of internal counters while in Parallel Interface Mode. A Counter bit0 (LSB). Enhancement register write enable. While E_WR is "high", Sdata can be serially clocked into the enhancement register on the rising edge of Sclk. Enhancement register write. D[7:0] are latched into the enhancement register on the rising edge of E_WR. A Counter bit1. M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising edge of M2_WR. A Counter bit2. Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface Mode (Bmode=0, Smode=0). A Counter bit3 (MSB). Selects direct interface mode (Bmode=1). Same as pin 1. M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the rising edge of M1_WR. A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge of A_WR. Hop write. The contents of the primary register are latched into the secondary register on the rising edge of Hop_WR. Prescaler input from the VCO. 3.0 GHz max frequency. Prescaler complementary input. A bypass capacitor in series with a 51 resistor should be placed as close as possible to this pin and be connected directly to the ground plane. Ground.
19
E_WR Parallel A1 M2_WR A2 Smode A3 Direct Parallel Direct Serial, Parallel Direct ALL ALL Parallel Parallel Serial, Parallel ALL ALL ALL ALL Output
20
21
22 23 24 25 26 27 28 29 30
Bmode
VDD M1_WR A_WR Hop_WR Fin
Fin
GND fp
Monitor pin for main divider output. Switching activity can be disabled through enhancement register programming or by floating or grounding VDD pin 31.
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Pin No.
31 32 33 34 35 36 37 38 39 40 41 42 43 44
Note 1: Note 2:
Pin Name
VDD-fp Dout VDD Cext VDD PD_D PD_U VDD-fc fc GND GND fr LD
Enh
Interface Mode
ALL Serial, Parallel ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL Serial, Parallel
Type
(Note 1) Output (Note 1) Output (Note 1) Output
Description
VDD for fp. Can be left floating or connected to GND to disable the fp output. Data Out. The MSEL signal and the raw prescaler output are available on Dout through enhancement register programming. Same as pin 1. Logical "NAND" of PD_U and PD_D terminated through an on chip, 2 k series resistor. Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier used for driving LD. Same as pin 1. PD_D is pulse down when fp leads fc. PD_U is pulse down when fc leads fp.
(Note 1) Output
VDD for fc. Can be left floating or connected to GND to disable the fc output. Monitor pin for reference divider output. Switching activity can be disabled through enhancement register programming or by floating or grounding VDD pin 38. Ground. Ground.
Input Output, OD Input
Reference frequency input. Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high impedance, otherwise LD is a logic low ("0"). Enhancement mode. When asserted low ("0"), enhancement register bits are functional.
VDD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level. VDD pins 31 and 38 are used to enable test modes and should be left floating. All digital input pins have 70 k pull-down resistors to ground.
Copyright Peregrine Semiconductor Corp. 2003
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UTSi CMOS RFIC SOLUTIONS
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PE9702
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Table 2. Absolute Maximum Ratings
Symbol
VDD VI II IO Tstg
Electrostatic Discharge (ESD) Precautions
Units
V V mA mA
C
Parameter/Conditions
Supply voltage Voltage on any input DC into any input DC into any output Storage temperature range
Min
-0.3 -0.3 -10 -10 -65
Max
4.0 VDD + 0.3 +10 +10 150
When handling this UTSi device, observe the same precautions that you would use with other ESDsensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 4. Latch-Up Avoidance Unlike conventional CMOS devices, UTSi CMOS devices are immune to latch-up.
Table 3. Operating Ratings
Symbol
VDD TA
Parameter/Conditions
Supply voltage Operating ambient temperature range
Min
2.85 -40
Max
3.15 85
Units
V
C
Table 4. ESD Ratings
Symbol
VESD
Parameter/Conditions
ESD voltage (Human Body Model) - Note 1
Level
1000
Units
V
Note 1:
Periodically sampled, not 100% tested. Tested per MILSTD-883, M3015 C2
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Table 5. DC Characteristics
VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified Symbol
IDD
Parameter
Operational supply current; Prescaler disabled Prescaler enabled High level input voltage Low level input voltage High level input current Low level input current High level input current Low level input current High level input current Low level input current Output voltage LOW Output voltage HIGH Output voltage LOW, Cext Output voltage HIGH, Cext Output voltage LOW, LD
Conditions
VDD = 2.85 to 3.15 V
Min
Typ
10 24
Max
Units
mA mA V
31
Digital Inputs: All except fr, Fin, Fin VIH VIL IIH IIL IIHR IILR R0 Input: R0 IIHR IILR VOLD VOHD VOLC VOHC VOLLD VIH = VDD = 3.15 V VIL = 0, VDD = 3.15 V Iout = 6 mA Iout = -3 mA Iout = 100 mA Iout = -100 mA Iout = 6 mA VDD - 0.4 0.4 VDD - 0.4 0.4 -5 0.4 +70
A A
VDD = 2.85 to 3.15 V VDD = 2.85 to 3.15 V VIH = VDD = 3.15 V VIL = 0, VDD = 3.15 V VIH = VDD = 3.15 V VIL = 0, VDD = 3.15 V
0.7 x VDD 0.3 x VDD +70 -1 +100 -100
V
A A A A
Reference Divider input: fr
Counter and phase detector outputs: fc, fp. V V V V V
Lock detect outputs: Cext, LD
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Table 6. AC Characteristics
VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified Symbol
fClk tClkH tClkL tDSU tDHLD tPW tCWR tCE tWRC tEC tMDO Fin PFin Fin PFin Reference Divider fr Pfr Phase Detector fc
Note 1:
Parameter
Serial data clock frequency Serial clock HIGH time Serial clock LOW time Sdata set-up time after Sclk rising edge, D[7:0] set-up time to M1_WR, M2_WR, A_WR, E_WR rising edge Sdata hold time after Sclk rising edge, D[7:0] hold time to M1_WR, M2_WR, A_WR, E_WR rising edge S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width Sclk rising edge to S_WR rising edge. S_WR, M1_WR, M2_WR, A_WR falling edge to Hop_WR rising edge Sclk falling edge to E_WR transition S_WR falling edge to Sclk rising edge. Hop_WR falling edge to S_WR, M1_WR, M2_WR, A_WR rising edge E_WR transition to Sclk rising edge MSEL data out delay after Fin rising edge Operating frequency Input level range Operating frequency Input level range Operating frequency Reference input power (Note 2) Comparison frequency
Conditions
(Note 1)
Min
Max
10
Units
MHz ns ns ns ns ns ns ns ns ns
Control Interface and Latches (see Figures 3, 4, 5) 30 30 10 10 30 30 30 30 30 CL = 12 pf 500 External AC coupling -5 50 External AC coupling (Note 3) Single-ended input (Note 3) -2 20 -5 8 3000 5 300 5 100
ns MHz dBm MHz dBm MHz dBm MHz
Main Divider (Including Prescaler)
Main Divider (Prescaler Bypassed)
Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk specification. CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5Vp-p. Parameter is guaranteed through characterization only and is not tested.
Note 2: Note 3:
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Functional Description The PE9702 consists of a prescaler, counters, a phase detector, and control logic. The dual modulus prescaler divides the VCO frequency by either 10 or 11, depending on the value of the modulus select. Counters "R" and "M" divide the reference and prescaler output, respectively, by integer values stored in a 20-bit register. An additional counter ("A") is used in the modulus Figure 3. Functional Block Diagram
R Counter (6-bit)
select logic. The phase-frequency detector generates up and down frequency control signals. The control logic includes a selectable chip interface. Data can be written via serial bus, parallel bus, or hardwired directly to the pins. There are also various operational and test modes and a lock detect output.
fr
fc
D(7:0) Sdata Control Pins
Control Logic
R(5:0) M(8:0) A(3:0)
Phase Detector
PD_U PD_D LD Cext
Modulus Select
Fin Fin
10/11 Prescaler
M Counter (9-bit)
fp
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Main Counter Chain Normal Operating Mode The main counter chain divides the RF input frequency, Fin, by an integer derived from the userdefined values in the "M" and "A" counters. It is composed of the 10/11 dual modulus prescaler, modulus select logic, and 9-bit M counter. Setting Pre_en "low" enables the 10/11 prescaler. Setting Pre_en "high" allows Fin to bypass the prescaler and powers down the prescaler. The output from the main counter chain, fp, is related to the VCO frequency, Fin, by the following equation:
fp = Fin / [10 x (M + 1) + A] where A M + 1, 1 M 511 (1)
Reference Counter The reference counter chain divides the reference frequency, fr, down to the phase detector comparison frequency, fc. The output frequency of the 6-bit R Counter is related to the reference frequency by the following equation:
fc = fr / (R + 1) where 0 R 63 (4)
Note that programming R with "0" will pass the reference frequency, fr, directly to the phase detector. In Direct Interface Mode, R Counter inputs R4 and R5 are internally forced low ("0"). In this mode, the R value is limited to 0 R 15. Register Programming Parallel Interface Mode Parallel Interface Mode is selected by setting the Bmode input "low" and the Smode input "low". Parallel input data, D[7:0], are latched in a parallel fashion into one of three 8-bit primary register sections on the rising edge of M1_WR, M2_WR, or A_WR per the mapping shown in Table 7 on page 10. The contents of the primary register are transferred into a secondary register on the rising edge of Hop_WR according to the timing diagram shown in Figure 5. Data is transferred to the counters as shown in Table 7 on page 10. The secondary register acts as a buffer to allow rapid changes to the VCO frequency. This double buffering for "ping-pong" counter control is programmed via the FSELP input. When FSELP is "high", the primary register contents set the counter inputs. When FSELP is "low", the secondary register contents are utilized. Parallel input data, D[7:0], are latched into the enhancement register on the rising edge of E_WR according to the timing diagram shown in Figure 4. This data provides control bits as shown in Table 8 on page 10 with bit functionality enabled by asserting the Enh input "low".
When the loop is locked, Fin is related to the reference frequency, fr, by the following equation:
Fin = [10 x (M + 1) + A] x (fr / (R+1)) where A M + 1, 1 M 511 (2)
A consequence of the upper limit on A is that Fin must be greater than or equal to 90 x (fr / (R+1)) to obtain contiguous channels. Programming the M Counter with the minimum value of "1" will result in a minimum M Counter divide ratio of "2". In Direct Interface Mode, main counter inputs M7 and M8 are internally forced low. In this mode, the M value is limited to 1 M 127. Prescaler Bypass Mode Setting Pre_en "high" allows Fin to bypass and power down the prescaler. In this mode, the 10/11 prescaler and A register are not active, and the input VCO frequency is divided by the M counter directly. The following equation relates Fin to the reference frequency, fr:
Fin = (M + 1) x (fr / (R+1)) ) where 1 M 511 (3)
In Direct Interface Mode, main counter inputs M7 and M8 are internally forced low. In this mode, the M value is limited to 1 M 127.
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Serial Interface Mode Serial Interface Mode is selected by setting the Bmode input "low" and the Smode input "high". While the E_WR input is "low" and the S_WR input is "low", serial input data (Sdata input), B0 to B19, is clocked serially into the primary register on the rising edge of Sclk, MSB (B0) first. The contents from the primary register are transferred into the secondary register on the rising edge of either S_WR or Hop_WR according to the timing diagram shown in Figure 6. Data is transferred to the counters as shown in Table 7 on page 10. The double buffering provided by the primary and secondary registers allows for "ping-pong" counter control using the FSELS input. When FSELS is "high", the primary register contents set the counter inputs. When FSELS is "low", the secondary register contents are utilized. While the E_WR input is "high" and the S_WR input is "low", serial input data (Sdata input), B0 to B7, is
clocked serially into the enhancement register on the rising edge of Sclk, MSB (B0) first. The enhancement register is double buffered to prevent inadvertent control changes during serial loading, with buffer capture of the serially-entered data performed on the falling edge of E_WR according to the timing diagram shown in Figure 5. After the falling edge of E_WR, the data provides control bits as shown in Table 8 with bit functionality enabled by asserting the Enh input "low". Direct Interface Mode Direct Interface Mode is selected by setting the Bmode input "high". Counter control bits are set directly at the pins as shown in Table 7. In Direct Interface Mode, main counter inputs M7 and M8, and R Counter inputs R4 and R5 are internally forced low ("0").
Table 7. Primary Register Programming
Interface Mode Parallel Serial* Direct Enh 1 1 1 Bmode 0 0 1 Smode 0 1 X R5 R4 M8 M7 Pre_en M6 M5 M4 M3 M2 M1 M0 R3 R2 R1 R0 A3 A2 A1 A0
M2_WR rising edge load D3 B0 0 D2 B1 0 D1 B2 0 D0 B3 0 D7 B4 Pre_en D6 B5 M6
M1_WR rising edge load D5 B6 M5 D4 B7 M4 D3 B8 M3 D2 B9 M2 D1 B10 M1 D0 B11 M0 D7 B12 R3 D6 B13 R2
A_WR rising edge load D5 B14 R1 D4 B15 R0 D3 B16 A3 D2 B17 A2 D1 B18 A1 D0 B19 A0
*Serial data clocked serially on Sclk rising edge while E_WR "low" and captured in secondary register on S_WR rising edge.
MSB (first in)
(last in) LSB
Table 8. Enhancement Register Programming
Interface Mode Parallel Serial* Enh 0 0 Bmode 0 0 Smode 0 1 Reserved Reserved Reserved Power down Counter load MSEL output Prescaler output fc, fp OE
E_WR rising edge load D7 B0 D6 B1 D5 B2 D4 B3 D3 B4 D2 B5 D1 B6 D0 B7
*Serial data clocked serially on Sclk rising edge while E_WR "high" and captured in the double buffer on E_WR falling edge.
MSB (first in)
(last in) LSB
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Figure 4. Parallel Interface Mode Timing Diagram
tDSU tDHLD
D [7 : 0]
tPW tCWR tWRC
M1_WR M2_WR A_WR E_WR
tPW
Hop_WR
Figure 5. Serial Interface Mode Timing Diagram
Sdata
E_WR
tEC tCE
Sclk
S_WR
tDSU tDHLD tClkH tClkL tCWR tPW tWRC
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Enhancement Register The functions of the enhancement register bits are shown below with all bits active "high". Table 9. Enhancement Register Bit Functionality
Bit Function
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Reserved** Reserved** Reserved** Power down Counter load MSEL output Prescaler output fp, fc OE Power down of all functions except programming interface. Immediate and continuous load of counter programming as directed by the Bmode and Smode inputs. Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output. Drives the raw internal prescaler output (fmain) onto the Dout output. fp, fc outputs disabled.
Description
** Program to 0
Phase Detector The phase detector is triggered by rising edges from the main Counter (fp) and the reference counter (fc). It has two outputs, namely PD_U, and PD_D. If the divided VCO leads the divided reference in phase or frequency (fp leads fc), PD_D pulses "low". If the divided reference leads the divided VCO in phase or frequency (fr leads fp), PD_U pulses "low". The width of either pulse is directly proportional to phase offset between the two input signals, fp and fc. The phase detector gain is 430 mV / radian. PD_U and PD_D are designed to drive an active loop filter which controls the VCO tune voltage. PD_U pulses result in an increase in VCO frequency and PD_D results in a decrease in VCO frequency. A lock detect output, LD is also provided, via the pin Cext. Cext is the logical "NAND" of PD_U and PD_D waveforms, which is driven through a series 2k ohm resistor. Connecting Cext to an external shunt capacitor provides integration. Cext also drives the input of an internal inverting comparator with an open drain output. Thus LD is an "AND" function of PD_U and PD_D. See Figure 3 for a schematic of this circuit.
Copyright Peregrine Semiconductor Corp. 2003
File No. 70/0036~00C |
UTSi CMOS RFIC SOLUTIONS
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PE9702
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Figure 6. Package Drawing
44-lead CQFJ
All dimensions are in mils
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Table 10. Ordering Information
Order Code
9702-01 9702-11 9702-00
Part Marking
PE9702 ES PE9702 PE9702 EK
Description
Engineering Samples Flight Units Evaluation Kit
Package
44-pin CQFJ 44-pin CQFJ
Shipping Method
40 units / Tray 40 units / Tray 1 / Box
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